
`include "common_header.verilog"

//  *************************************************************************
//  File : decode64_dp.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2012 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//  Description : Clause 82 decoder datapath (192bit) toplevel combining 
//                descrambler, decoder and test pattern checker.
//  Version     : $Id: decode64_dp.v,v 1.5 2016/07/13 06:58:13 dk Exp $
//  *************************************************************************

module decode64_dp (

        reset,
        clk,
        clk_ena,
        data_0_in,
        sh_0_in,
	scr_bypass,
	ena_clause49,
        loopback_ena,
        cgmii_txclk_ena,
        cgmii_txc,
        cgmii_txd,
        r_test_mode,
        en_chk_pat49,
        sel_pat,
        block_lock,
        hi_ber,
`ifdef MTIP_DEBUG_BUSES
        decode_val,
        dec_error,        
`endif
`ifdef MTIPPCS_EEE_ENA
        rx_lpi_active,
        r_type_li,
        r_type_c,
        r_type_val,
`endif

        err_block_count_rd,
        err_block_count,
        pat_err_cnt_rd,
        pat_err_cnt,
        rx_d_out,
        rx_c_out,
        xlgmii_rxt0_next,
        rx_val_out);

input           reset;                  //  asynch reset
input           clk;                    //  system clock
input           clk_ena;                //  clock enable (data from MLD valid)
input   [63:0]  data_0_in;              //  data input from MLD
input   [1:0]   sh_0_in;                //  sync header

input           scr_bypass;             // bypass scrambling and descrambling within PCS
input  		ena_clause49;		//  Enable Clause 49 (1) or Clause 82 (0) PCS encoder/decoder 
input           loopback_ena;           //  XL/CGMII loopback enable
input           cgmii_txclk_ena;        //  XL/CGMII clock enable to control loopback
input   [7:0]   cgmii_txc;              //  XL/CGMII transmit control
input   [63:0]  cgmii_txd;              //  XL/CGMII transmit data
input           r_test_mode;            //  Receive test pattern mode
input           en_chk_pat49;           //  Enable 10G Test pattern checker (49.2.12) 
input           sel_pat;                //  Select pattern : 1 => 00 / 0 => Local Fault 
input           block_lock;             //  Lock state reached
input           hi_ber;                 //  High Bit Error
`ifdef MTIP_DEBUG_BUSES
output          decode_val;             // if 1 decoding is possible, otherwise local fault is generated
output  [2:0]   dec_error;              //  per block decode error indication           
`endif
input           err_block_count_rd;     //  Block error counter has been read
output  [21:0]  err_block_count;        //  Block error counter to be read
input           pat_err_cnt_rd;         //  test pattern error counter has been read
output  [15:0]  pat_err_cnt;            //  test pattern error counter
output  [63:0]  rx_d_out;               //  data to XL/CGMII bus
output  [7:0]   rx_c_out;               //  control to from XL/CGMII bus
output          xlgmii_rxt0_next;       //  Advance indication if TERM block without data is next after current 
                                        // (directly from decoder classification block type 0x87, T0)       

output          rx_val_out;             //  output valid (clock-enable out)
`ifdef MTIPPCS_EEE_ENA
input           rx_lpi_active;          // True when the RS-FEC sublayer infers that the Low Power Idle is being received from the link partner and is set to false otherwise.
output          r_type_li;              // LPI Block Received
output          r_type_c;               // C block Received
output          r_type_val;             // data_val(clk enable) for the r_type_li and r_type_c

wire            r_type_li;
wire            r_type_c;
wire            r_type_val;

`endif

wire    [21:0]  err_block_count; 
wire    [15:0]  pat_err_cnt; 
wire    [63:0]  rx_d_out; 
wire    [7:0]   rx_c_out; 
wire            xlgmii_rxt0_next;
wire            rx_val_out; 
reg             clk_ena_d;              //  1 delayed
wire    [1:0]   sh_out_0;               //  Sync header      (registered copy of input)
wire    [63:0]  dout_0;                 //  Descrambled output data
`ifdef MTIP_DEBUG_BUSES
wire            decode_val;             // if 1 decoding is possible, otherwise local fault is generated
wire            dec_error;              //  per block decode error indication           
`endif

//  Use Descrambler as pipeline
//  ---------------------------

descrmbl64 U_DSC64 (

        .reset          (reset),
        .clk            (clk),
        .clk_ena        (clk_ena),
        .scr_bypass     (scr_bypass),
        .sh_in_0        (sh_0_in),
        .din_0          (data_0_in),
        .sh_out_0       (sh_out_0),
        .dout_0         (dout_0));

//  descrambler output is valid 1 cycle later.

always @(posedge reset or posedge clk)
begin : pcke1
        if (reset == 1'b 1)
        begin
                clk_ena_d <= 1'b 0;	
        end
        else
        begin
                clk_ena_d <= clk_ena;	
        end
end

//  Decoder as pipeline
//  ---------------------------
decode64 U_DEC64 (

        .reset                  (reset),
        .clk                    (clk),
        .ck_ena                 (clk_ena_d),          //  follows descrambler
        .data_0_in              (dout_0),
        .sh_0_in                (sh_out_0),
        .ena_clause49		(ena_clause49),
        .loopback_ena           (loopback_ena),
        .cgmii_txclk_ena        (cgmii_txclk_ena),
        .cgmii_txc              (cgmii_txc),
        .cgmii_txd              (cgmii_txd),
        .r_test_mode            (r_test_mode),
        .block_lock             (block_lock),
        .hi_ber                 (hi_ber),
`ifdef MTIP_DEBUG_BUSES
        .decode_val             (decode_val),
        .dec_error              (dec_error),        
`endif
`ifdef MTIPPCS_EEE_ENA
        .rx_lpi_active          (rx_lpi_active),
        .r_type_li              (r_type_li),
        .r_type_c               (r_type_c),
        .r_type_val             (r_type_val),
`endif
        .err_block_count_rd     (err_block_count_rd),
        .err_block_count        (err_block_count),
        .rx_d_out               (rx_d_out),
        .rx_c_out               (rx_c_out),
        .xlgmii_rxt0_next       (xlgmii_rxt0_next),
        .rx_val_out             (rx_val_out));

//  Test Pattern Checker. Operates after Descrambler
//  -------------------------------------------
check_pat824964 U_CPAT64 (

        .reset                  (reset),
        .clk                    (clk),
        .clk_ena                (clk_ena_d),        //  follows Descrambler
        .r_test_mode            (r_test_mode),
        .en_chk_pat49           (en_chk_pat49),
        .sel_pat                (sel_pat),
        .block_lock             (block_lock),
        .data_in                (dout_0),
        .sh_in                  (sh_out_0),
        .pat_err_cnt_rd         (pat_err_cnt_rd),
        .pat_err_cnt            (pat_err_cnt));

endmodule // module decode64_dp

